1. Field of the Invention
This invention relates to semiconductor manufacturing and, more particularly, to the use of a germanium doped silicate glass as a spacer oxide and as a replacement for Boron-Phosphorous-Silicate-Glass (BPSG) interlevel insulators.
2. Description of the Prior Art
Integrated circuits are typically manufactured by depositing a variety of films on a silicon substrate and then subjecting the films to various processing steps. One typical structure is illustrated in FIG. 1. FIG. 1 depicts two integrated circuit features 3 constructed on a silicon substrate 1, each capped by an insulator 19 and covered by an insulating layer 5 of undoped oxide. An xe2x80x9cintegrated circuit featurexe2x80x9d for present purposes includes all manner of geometric structures that may be disposed on a substrate and includes, but is not limited to, transistor gates, metal lines, interconnects, capacitors, nodes, and leads. The particular features 3 illustrated in FIG. 1 happen to be transistor gates. The gates of FIG. 1 are integrated circuit features created by depositing layers of assorted materials and then etching away portions of the deposited layers. The insulating layer 5 of undoped oxide helps to insulate the features from other conductive materials that might, and probably will, be deposited over the structure of FIG. 1.
The insulating layer 5 of FIG. 1 has xe2x80x9cretrograde wall profilesxe2x80x9d 7. A retrograde wall profile is a wall profile that is not vertical and generally includes some overhang such that the layer is wider on the top of an integrated circuit feature than it is on the bottom. The particular retrograde wall profiles 7 of the insulating layer 5 in FIG. 1 result from an effect called xe2x80x9cbreadloafing.xe2x80x9d Breadloafing is a characteristic of some deposition techniques whereby the deposited insulator is thicker at the tops and corners of the structure and thinner along the sides and is denoted by the numeral 9 in FIG. 1.
One problem associated with retrograde wall profiles 7 is that materials subsequently deposited in a conformal manner over the retrograde wall will also have retrograde wall profiles. xe2x80x9cIn a conformal mannerxe2x80x9d means in a way that mirrors or reflects the topography of the material layer on which the current layer is being deposited. For example, it is common in stacked DRAM capacitors to subsequently deposit a layer of polysilicon 4 over the insulator layer to form the storage node of the capacitor. If the insulating layer is retrograde, and because the polysilicon etch is typically anisotropic, it will be difficult to remove the polysilicon that remains under the overhang portion of the insulating layer. As shown in FIG. 2, the result is an unwanted poly xe2x80x9cstringerxe2x80x9d 17. If the stringer material is conductive, as in the case of polysilicon 4, it may lead to electrical shorts in the circuitry.
It is known in the art that these problems associated with retrograde wall profiles worsen in proportion with the aspect ratio, i.e., the ratio between the height and width of the integrated circuit features. Features having high aspect ratio, retrograde topologies therefore are very susceptible to stringers. It is therefore desirable to have prograde, or outwardly sloping, wall profiles as opposed to retrograde wall profiles.
One approach to obtain effectively prograde wall profiles called xe2x80x9cfacet etchingxe2x80x9d is illustrated in FIG. 3. More particularly, after the feature is constructed, a process step etches facets 8 in the top comers of the feature 3 and allows the material 11 etched away to be redeposited in the spaces surrounding the structure. If the etched away material 11 is electrically conductive and of the right composition, it can be oxidized into an insulator. If the etched away material is insulative, as in the case illustrated, this step is unnecessary. The effectively prograde wall profiles 13 generates by this technique produce prograde wall profiles 15 in layers subsequently deposited thereover, as is evident from FIG. 3. There are several variations on this theme and two such techniques are disclosed in U.S. Pat. Nos. 5,416,048 and 5,346,585. These references are hereby expressly incorporated by reference for all permissible purposes as if set forth verbatim herein.
However, facet etching has several undesirable consequences. Facet etching is an expensive and time consuming process step, and consequently raises overall processing costs. Facet etching also introduces contaminants into the process unless tightly controlled. Thus, it is desirable to find a new technique for obtaining prograde or effectively prograde wall profiles.
In one aspect of the present invention a method is provided for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon.